As integrated circuits become more complex, it becomes increasingly necessary to implement thorough testing for verifying functionality and conformance to specifications. At the same time the shrinking size of integrated circuits as well as the accelerating speed requirements of devices have propelled the development of smaller and faster testing methods. Various standards bodies have also been involved in developing test standards in an effort towards promoting standardization of test methods. To this end a “boundary-scan” testing specification was proposed and developed by the Joint Test Action Group (JTAG) which was later standardized as the IEEE standards 1149.1 specification. This boundary-scan test architecture offers the capability to test components efficiently whether embedded in assembled printed circuit board assemblies or in the form of integrated circuit devices.
The Boundary Scan Test architecture is capable of testing pin connections without using physical test probes. It is also capable of capturing functional data while a device is in normal operation. The boundary scan process can force signals onto pins, or capture data from pin or core logic signals. Captured test data is serially shifted into special boundary scan cells from where it can be serially shifted out and compared to expected results externally.
Boundary scan register cells are placed such that the state of each digital system pin can be controlled or observed using the boundary scan register. These cells may also allow the state of the system logic inputs and outputs to be controlled and observed respectively.
While the implementation of conventional IEEE 1149.1 compliant interfaces within components, such as integrated circuit chips, facilitates higher quality, low cost testing without the need for disclosure of the internal circuitry of the components under test, these benefits come at the expense of performance due to the signal path delay associated with boundary scan cells. Because of the performance penalty associated with conventional IEEE 1149.1-compliant boundary scan cells manufacturers have resisted compliance with the IEEE 1149.1 standard.
U.S. Pat. No. 6,266,793, proposes a method for boundary scanning with increased testability by adding one extra signal to the standard methods, so that input buffers and output buffers are also testable in a two bit bi-directional boundary scan cell. However this method can not be implemented with the standard “INTEST” instruction defined by IEEE standard 1149.1.